1. Field of the Invention
The present invention relates to an A/D converter that operates at high speed necessary for digitizing a reproduction signal of a hard disk, a comparator that accomplishes such an A/D converter, and a differential amplifier that accomplishes such a comparator.
2. Description of the Related Art
As the speed of a signal process increases, a high speed A/D converter is desired. For example, a hard disk drive has an A/D converter that digitizes a reproduction signal of a head is disposed so as to perform an equalizing process and a Viterbi decoding process. As the speed of a hard disk drive increases, an A/D converter having 6 to 8 quantizing bits having a sampling clock signal frequency of several 100 MHz (for example, 400 MHz) is desired.
An A/D converter compares an input voltage with a reference voltage and encodes the compared voltage so as to convert an analog signal into a digital signal. As was described above, to accomplish an A/D converter that operates at high speed, a comparator should be composed of a differential amplifier having a high gain and a wide frequency band.
Conventionally, an analog circuit that operates at high speed is composed of bipolar transistors. Thus, a differential amplifier having a high gain and a wide frequency band may be composed of bipolar transistors.
However, the power consumption of a bipolar transistor is large. In addition, a bipolar transistor cannot be integrated with another signal processing circuit as an integrated circuit. Thus, it is strongly desired to accomplish a differential amplifier having a high gain and a wide frequency band with CMOS transistors.
Parameters that allow a differential amplifier composed of CMOS transistors to have a high gain and a wide frequency band are the current and the size because gm (mutual conductance) of an MOS transistor depends on the current that flows therein and the size thereof. Thus, to accomplish a differential amplifier having a high gain, it is necessary to set a high current value or increase the size of each MOS transistor.
When the current that flows in a MOS transistor is increased, the power consumption is adversely increased. When the size of a MOS transistor is increased, the parasitic capacitance is increased. Thus, a wide frequency band cannot be accomplished.
In a differential circuit composed of bipolar transistors, a compensating circuit is disposed. The compensating circuit generates a compensation current that flows in the reverse direction of a current that flows in a capacitance CBC formed between the base and the collector of each bipolar transistor. The compensation current cancels a current that flows between the base and the collector of the bipolar transistor. As a result, the problem of the band limitation due to the parasitic capacitance can be solved. Thus, a differential amplifier having a wide frequency band is accomplished. Such a technique is proposed in xe2x80x9cA Low-Power Wide-Band Amplifier Using a New Parasitic Capacitance Compensation Techniquexe2x80x9d, IEEE Journal of Solid-State Circuit, Vol. 121, No. 1, February 1990.
When a differential amplifier having a high gain and a wide frequency band is accomplished using CMOS transistors, such a technique may be used. As was described above, when the size of each MOS transistor is increased, a high gain can be obtained. In that case, the parasitic capacitance is increased. When the technique for canceling the current that flows in the parasitic capacitance with the compensation current is applied to a CMOS structure, a CMOS differential amplifier having a high gain and a wide frequency band is accomplished. Thus, using such a differential amplifier, a high speed A/D converter can be accomplished.
As shown in FIG. 1, when an amplifier is considered as a model of which a network of a resistor R and a capacitor C is driven by a signal source Vi having a signal source resistor RS, the following formula can be obtained.                               G          0                =                                            R              s                        //            R                                R            S                                              (        1        )                                          f                      3            ⁢            dB                          =                  1                      2            ⁢                          piC              ⁡                              (                                  R                  //                                      R                    S                                                  )                                                                        (        2        )                                                      G            0                    ⁢          B                =                                            G              0                        ⁢                          f                              3                ⁢                dB                                              =                      1                          2              ⁢                              PiCR                S                                                                        (        3        )            
where G0 is a DC gain; f3 dB is a frequency band that lowers by 3 dB; pi is xcex4 (ratio of circumference of circle to its diameter); and G0B is a gain bandwidth.
As expressed in Formula (3), the frequency band depends on the capacitance C and the resistance RS of the signal source. In the case of a bipolar transistor, the capacitance C that limits the frequency band is equivalent to the capacitance CBC formed between the base and the collector of the bipolar transistor. Since the capacitance CBC formed between the base and the collector of the bipolar transistor is amplified by the mirror effect. Thus, the capacitance CBC largely affects the decrease of the frequency band.
As shown in FIG. 2, to solve such a problem, a current source sCCVO (where s: Laplace operator) that varies corresponding to the output voltage VO is disposed on the output side. The current sCCVO cancels the current that flows in the capacitance C. In that case, the following formulas can be obtained.                               G          0                =                                            R              s                        //            R                                R            S                                              (        4        )                                          f                      3            ⁢            dB                          =                  1                      2            ⁢                          Pi              ⁡                              (                                  C                  -                                      C                    c                                                  )                                      ⁢                          (                              R                //                                  R                  s                                            )                                                          (        5        )                                                      G            0                    ⁢          B                =                                            G              0                        ⁢                          f                              3                ⁢                dB                                              =                      1                          2              ⁢                              Pi                ⁡                                  (                                      C                    -                                          C                      c                                                        )                                            ⁢                              R                s                                                                        (        6        )            
Assuming that C=Cs, the denominator becomes 0. Thus, it is clear that the frequency band is not limited.
FIG. 3 shows an example of the structure of a differential amplifier using bipolar transistors, each of which having a current that flows in a capacitance formed between the base and the collector that is canceled with a compensation current corresponding to an output voltage so as to widen the frequency band.
In FIG. 3, the emitters of NPN transistors 201 and 202 are connected. The emitters of the transistors 201 and 202 are connected to a ground line 204 through a current source 203. Input terminals 221 and 222 are connected to the bases of the transistors 201 and 202.
The collectors of the transistors 201 and 202 are connected to a power line 207 through resistors 205 and 206, respectively. In addition, the collectors of the transistors 201 and 202 are connected to the bases of transistors 208 and 209, respectively. The collectors of the transistors 208 and 209 are connected to the power line 207. The emitters of transistors 208 and 209 are connected to the ground line 204 through current sources 210 and 211, respectively. In addition, the emitters of the transistors 208 and 209 are connected to output terminals 223 and 224, respectively.
In addition, the emitters of the transistors 208 and 209 are connected to the bases of transistors 212 and 213, respectively. The collectors of the transistors 212 and 213 are connected to the collectors of the transistors 202 and 201, respectively. The emitters of the transistors 212 and 213 are connected to the ground line 204 through current sources 214 and 215, respectively. In addition, a capacitor 216 is connected between the emitter of the transistor 212 and the emitter of the transistor 213.
In FIG. 3, a difference input voltage that is input from the input terminals 221 and 222 is amplified by the transistors 201 and 202. The amplified voltage is output from the output terminals 223 and 224 through the emitter follower transistors 208 and 209, respectively.
In addition, the output voltage takes place between the emitters of the transistors 212 and 213 through an emitter follower circuit composed of the transistors 212 and 213. A current corresponding to the output voltage flows in the capacitor 216 connected between the emitters of the transistors 212 and 213.
As shown in FIG. 4, when the capacitor 216 is composed of transistors 231 and 232 that are similar to the transistors 201 and 202 that compose the differential pair, the capacitance CC of the capacitor 216 becomes almost the same as the capacitance CCB between the base and the collector of each of the transistors 201 and 202.
Thus, the capacitor 216 forms a compensation current that is equal to the current that flows in each of the transistors 201 and 202. When the collectors of the transistors 212 and 213 are connected to the collectors of the transistors 202 and 201, respectively, the current that flows in the capacitance CCB formed between the base and the collector of each of the transistors 201 and 202 is canceled by the compensation current that flows in the capacitor 216. Thus, a differential amplifier having a high gain and a wide frequency band free of the limitation thereof can be accomplished.
As shown in FIG. 3, the output voltages of the transistors 201 and 202 as a differential pair are supplied to the capacitor 216 through the emitter follower transistors 208 and 209 and the emitter follower transistors 212 and 213, respectively. The capacitor 216 disposed between the emitters of the transistors 212 and 213 generates a compensation current that is equal to a current that flows in the capacitance CBC formed between the base and the collector of each of the transistors 201 and 202 as a differential pair. The compensation current causes the current that flows in the capacitance CBC formed between the base and the collector of each of the transistors 201 and 202 as a differential pair to be canceled. Thus, the differential circuit can be free of the limitation of the frequency band.
However, in such a structure, the compensation current is generated corresponding to the output signal voltage detected through the emitter follower transistors 208 and 209 and the emitter follower transistors 212 and 213. Thus, when such a circuit is composed of CMOS transistors, a level shift of 2 VGS takes place (where VGS is the voltage between the gate and the source) due to the compensation current. On the other hand, when such a circuit is composed of MOS transistors, since the voltage VGS between the gate and source is around 1 V, a level shift of around 2 V takes place in the portion that generates the compensation current.
On the other hand, a low voltage power supply structure is becoming the mainstream. In a low voltage circuit, a power supply of for example 3.3 V is used. When a level shift of 2 V takes place in such a low voltage circuit, a sufficient amplitude of signals cannot be secured.
On the other hand, when such a circuit is composed of CMOS transistors, the gain of the source follower of MOS transistors does not become one time due to an influence of the substrate effect. Thus, as was described above, when an output signal voltage is detected through two stages of the follower transistors 208 and 209 and the follower transistors 212 and 213, the amplitude of a detected output voltage is decreased. Consequently, the effect for canceling the parasitic capacitance deteriorates.
Therefore, an object of the present invention is to provide a differential amplifier that has a high gain and a wide frequency band and that operates at low power supply voltage.
Another object of the present invention is to provide a comparator that operates at high speed.
A further object of the present invention is to provide an A/D converter that operates at high speed.
A first aspect of the present invention is a differential amplifier, comprising a differential pair composed of a first transistor and a second transistor whose sources or emitters are connected in common, a buffer means for extracting an output of said differential pair composed of the first transistor and the second transistor, and a compensation current generating means for generating a compensation current that is equal to a current that flows in a parasitic capacitance of each of the first transistor and the second transistor, the direction of the compensation current being the reverse of the current that flows in the parasitic capacitance, wherein said compensating circuit generating means is composed of a voltage input-current output means comprising a third transistor and a fourth transistor, a capacitor equivalent to the parasitic capacitance of each of the first transistor and the second transistor being connected between the sources or the emitters of the third transistor and the fourth transistor, a first current source and a second current source connected to the sources or the emitters of the third transistor and the fourth transistor, and a third current source and a fourth current source connected to the drains or the collectors of the third transistor and the fourth transistor, wherein output voltages of the first transistor and the second transistor are supplied to the gates or the bases of the third transistor and the fourth transistor, and wherein output currents of the drains or the collectors of the fourth transistor and the third transistor are supplied as compensation currents to the drains or the collectors of the second transistor and the first transistor.
A second aspect of the present invention is a comparator, comprising an amplifier, a means for causing the comparator to operate in an auto zero mode and an amp mode, the auto zero mode causing the offset of said amplifier to be canceled, the amp mode causing the input signal to be amplified and output, a means for inputting the input voltage in the auto zero mode and storing the input voltage to a capacitor connected to an input stage of said amplifier, a means for inputting a reference voltage in the amp mode, obtaining the differential voltage between the input voltage stored in the capacitor connected to the input stage of said amplifier and the reference voltage, and outputting the differential voltage from said amplifier, wherein said amplifier comprises a differential pair composed of a first transistor and a second transistor whose sources or emitters are connected in common, a buffer means for extracting an output of the differential pair composed of the first transistor and the second transistor, and a compensation current generating means for generating a compensation current that is equal to a current that flows in a parasitic capacitance of each of the first transistor and the second transistor, the direction of the compensation current being the reverse of the current that flows in the parasitic capacitance, wherein the compensating circuit generating means is composed of a voltage input-current output means comprising a third transistor and a fourth transistor, a capacitor equivalent to the parasitic capacitance of each of the first transistor and the second transistor being connected between the sources or the emitters of the third transistor and the fourth transistor, a first current source and a second current source connected to the sources or the emitters of the third transistor and the fourth transistor, and a third current source and a fourth current source connected to the drains or the collectors of the third transistor and the fourth transistor, wherein output voltages of the first transistor and the second transistor are supplied to the gates or the bases of the third transistor and the fourth transistor, and wherein output currents of the drains or the collectors of the fourth transistor and the third transistor are supplied as compensation currents to the drains or the collectors of the second transistor and the first transistor.
A third aspect of the present invention is a comparator, comprising an amplifier, a means for causing the comparator to operate in an auto zero mode and an amp mode, the auto zero mode causing the offset of said amplifier to be canceled, the amp mode causing the input signal to be amplified and output, a means for inputting a reference voltage in the auto zero mode and storing the reference voltage to a capacitor connected to an input stage of said amplifier, a means for inputting an input voltage in the amp mode, obtaining the differential voltage between the reference voltage stored in the capacitor connected to the input stage of said amplifier and the input voltage, and outputting the differential voltage from said amplifier, wherein said amplifier comprises a differential pair composed of a first transistor and a second transistor whose sources or emitters are connected in common, a buffer means for extracting an output of the differential pair composed of the first transistor and the second transistor, and a compensation current generating means for generating a compensation current that is equal to a current that flows in a parasitic capacitance of each of the first transistor and the second transistor, the direction of the compensation current being the reverse of the current that flows in the parasitic capacitance, wherein the compensating circuit generating means is composed of a voltage input-current output means comprising a third transistor and a fourth transistor, a capacitor equivalent to the parasitic capacitance of each of the first transistor and the second transistor being connected between the sources or the emitters of the third transistor and the fourth transistor, a first current source and a second current source connected to the sources or the emitters of the third transistor and the fourth transistor, and a third current source and a fourth current source connected to the drains or the collectors of the third transistor and the fourth transistor, wherein output voltages of the first transistor and the second transistor are supplied to the gates or the bases of the third transistor and the fourth transistor, and wherein output currents of the drains or the collectors of the fourth transistor and the third transistor are supplied as compensation currents to the drains or the collectors of the second transistor and the first transistor.
A fourth aspect of the present invention is an A/D converter, comprising a reference voltage generating means for generating a plurality of reference voltages that designate quantizing levels, a plurality of comparators for comparing each of the reference voltages and an input voltage, a plurality of latches for latching an output of each of said plurality of comparators, a decoder for generating a digital value corresponding to the input voltage with the output of each of said plurality of latches, wherein each of said plurality of comparators comprises an amplifier, a means for causing the comparator to operate in an auto zero mode and an amp mode, the auto zero mode causing the offset of the amplifier to be canceled, the amp mode causing the input signal to be amplified and output, a means for inputting the input voltage in the auto zero mode and storing the input voltage to a capacitor connected to an input stage of the amplifier, a means for inputting a reference voltage in the amp mode, obtaining the differential voltage between the input voltage stored in the capacitor connected to the input stage of the amplifier and the reference voltage, and outputting the differential voltage from the amplifier, wherein the amplifier comprises a differential pair composed of a first transistor and a second transistor whose sources or emitters are connected in common, a buffer means for extracting an output of the differential pair composed of the first transistor and the second transistor, and a compensation current generating means for generating a compensation current that is equal to a current that flows in a parasitic capacitance of each of the first transistor and the second transistor, the direction of the compensation current being the reverse of the current that flows in the parasitic capacitance, wherein the compensating circuit generating means is composed of a voltage input-current output means comprising a third transistor and a fourth transistor, a capacitor equivalent to the parasitic capacitance of each of the first transistor and the second transistor being connected between the sources or the emitters of the third transistor and the fourth transistor, a first current source and a second current source connected to the sources or the emitters of the third transistor and the fourth transistor, and a third current source and a fourth current source connected to the drains or the collectors of the third transistor and the fourth transistor, wherein output voltages of the first transistor and the second transistor are supplied to the gates or the bases of the third transistor and the fourth transistor, and wherein output currents of the drains or the collectors of the fourth transistor and the third transistor are supplied as compensation currents to the drains or the collectors of the second transistor and the first transistor.
A fifth aspect of the present invention is an A/D converter, comprising a reference voltage generating means for generating a plurality of reference voltages that designate quantizing levels, a plurality of comparators for comparing each of the reference voltages and an input voltage, a plurality of latches for latching an output of each of said plurality of comparators, a decoder for generating a digital value corresponding to the input voltage with the output of each of said plurality of latches, wherein each of said comparator comprises an amplifier, a means for causing the comparator to operate in an auto zero mode and an amp mode, the auto zero mode causing the offset of the amplifier to be canceled, the amp mode causing the input signal to be amplified and output, a means for inputting a reference voltage in the auto zero mode and storing the reference voltage to a capacitor connected to an input stage of the amplifier, a means for inputting an input voltage in the amp mode, obtaining the differential voltage between the reference voltage stored in the capacitor connected to the input stage of the amplifier and the input voltage, and outputting the differential voltage from the amplifier, wherein the amplifier comprises a differential pair composed of a first transistor and a second transistor whose sources or emitters are connected in common, a buffer means for extracting an output of the differential pair composed of the first transistor and the second transistor, and a compensation current generating means for generating a compensation current that is equal to a current that flows in a parasitic capacitance of each of the first transistor and the second transistor, the direction of the compensation current being the reverse of the current that flows in the parasitic capacitance, wherein the compensating circuit generating means is composed of a voltage input-current output means comprising a third transistor and a fourth transistor, a capacitor equivalent to the parasitic capacitance of each of the first transistor and the second transistor being connected between the sources or the emitters of the third transistor and the fourth transistor, a first current source and a second current source connected to the sources or the emitters of the third transistor and the fourth transistor, and a third current source and a fourth current source connected to the drains or the collectors of the third transistor and the fourth transistor, wherein output voltages of the first transistor and the second transistor are supplied to the gates or the bases of the third transistor and the fourth transistor, and wherein output currents of the drains or the collectors of the fourth transistor and the third transistor are supplied as compensation currents to the drains or the collectors of the second transistor and the first transistor.
According to the present invention, an OTA circuit is disposed between a differential pair composed of NMOS transistors and an NMOS follower transistor that composes an output buffer circuit. The OTA circuit generates a compensation current that is equal to a current that flows in a capacitance formed between the gate and the drain of each of the differential pair transistors and that flows in the reverse direction thereof. The compensation current cancels the current that flows in the capacitance formed between the gate and the drain of each of the differential pair transistors. Thus, a differential amplifier that has a high accuracy and, high gain, and a wide frequency band and that operates at a low power voltage can be accomplished.
According to the present invention, using a differential amplifier having a high gain and a wide frequency band, a comparator that operates at high speed and an A/D converter using such a comparator can be accomplished.
These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of a best mode embodiment thereof, as illustrated in the accompanying drawings.